A clock transmission circuit is for transmitting clocks used in a semiconductor integrated circuit (LSI) to each circuit block using clocks from a clock oscillation source, and is widely utilized in various LSIs or the like that use clock signals, including communication LSI and CPU.
In other words, for example, the clock transmission circuit transmits clocks from a clock oscillation source to each circuit block, while maintaining the waveform of the clocks via a plurality of buffers.
Incidentally, in general, clock transmission by the clock transmission circuit is performed, for example, by application of a CMOS inverter or CML (Current Mode Logic). Since parasitic capacitance (load capacitance) is present in the wirings for transmitting clocks and the CMOS inverter (buffer), the load capacitance is charged and discharged during transmission of the clocks, so that the consumption current is increased. For example, when clock transmission is performed by application of CMOS inverter, the consumption current becomes proportional to the load capacitance and frequency.
Further, in recent years, as the processing speed and communication speed of a CPU are increased, the frequency of the internal clock in a LSI has been increased to several GHz or higher. Since the consumption current is proportional to the frequency as described above, when the frequency of the internal clock is increased to several GHz or higher, an increase in the consumption current in the clock transmission circuit becomes a problem.
As a method for performing clock transmission with low consumption power, a technique referred to as inductor peaking (Resonant Clock Distribution) has been proposed. Inductor peaking is also referred to as clock transmission by resonance.
Inductor peaking is a technique in which an inductor is, for example, located in parallel with the load capacitance to generate parallel resonance, so that the impedance seen by the buffer of the clock transmission circuit is increased and clock transmission is performed by making the load capacitance appear to be low.
Although, as described above, a clock transmission circuit for performing clock transmission using inductor peaking has been proposed, in such a clock transmission circuit, a common voltage (bias voltage) is, for example, applied by high resistance bias.
In other words, in order to set the common voltage to be a desired value, it has been the practice to add a capacitance or resistance element to the signal line for transmitting a high-speed signal (clock), for example, thereby providing a bias by an operational amplifier or resistor.
To reduce the influence on the transmitted clocks as much as possible, there is a technique to provide a bias via a high resistance element, i.e., a technique to set up the common voltage by increasing the impedance. Meanwhile, when the common voltage is set up by decreasing the impedance, a large influence is imparted to the transmitted differential (complementary) clocks, and therefore it is not usually practiced.
However, with the technique to provide a bias via high resistance elements, since the high resistance elements are formed in a semiconductor substrate (formed on a semiconductor chip), for example, addition of parasitic capacitance of several fF-several 100 fF is not avoidable, so that the band of the clock transmission circuit is reduced.
Further, when the impedance is increased, for example, increased susceptibility to external noise occurs, and in addition, jitter is caused in the transmitted clocks due to noise of the common voltage or a situation might occur in which the duty ratio is deviated.
Incidentally, in the past, various proposals have been made to perform clock transmission using an inductor peaking technique.
Patent Document 1: Japanese Laid-open Patent Publication No. H11(1999)-252185
Non-Patent Document 1: Fukuda et al., “A 12.3 mW 12.5 Gb/s Complete Transceiver in 65 nm CMOS,” Solid-State Circuits IEEE International Conference-ISSCC, pp. 368-369, February, 2010